1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a flash memory, i.e., a nonvolatile semiconductor memory device having electrically and collectively erasable characteristics.
2. Description of the Related Art
Recently, in accordance with popularization of computers, word processors, and the like, a plurality of semiconductor memory devices, typically non-volatile semiconductor memory devices, e.g., flash memory, used in such information processors, have been developed and produced.
The flash memory, which is one kind of non-volatile semiconductor memory device, can be made programmable by the user. Further, the flash memory can be rewritten by electrically and collectively erasing the stored data, and then by programming. Therefore, the flash memories have attracted considerable attention as a replacement for magnetic storage devices because they are suitable for integration. Note, there is a necessity of improving redundant circuits, write circuits, and overerasing preventive measures for such a flash memory.
An object of a first aspect of the present invention is to provide a semiconductor memory device for realizing effective word line redundancy and stable write and verify operations in a semiconductor memory device, to improve the yield and performance of the semiconductor memory device.
An object of a second aspect of the present invention is to provide a semiconductor memory device for reducing the size of the semiconductor memory device, to improve the yield of large capacity semiconductor memories and reduce the cost thereof.
An object of a third aspect of the present invention is to provide a semiconductor memory device for carrying out a delivery test of a semiconductor memory device with xe2x80x9cnxe2x80x9d rewrite operations at the maximum, and taking into account deterioration due to an increase in the number of rewrite operations, to guarantee the maximum rewrite operations N (N greater than n) for a user.
An object of a fourth aspect of the present invention is to provide a semiconductor memory device that is capable of supplying a write drain voltage that is not influenced by the threshold voltage of a write voltage supply transistor, thereby correctly writing data to a memory cell even with a low write voltage.
An object of a fifth aspect of the present invention is to provide a semiconductor memory device that correctly reads data even if there is an overerased cell transistor.
An object of a sixth aspect of the present invention is to provide a semiconductor memory device that correctly reads data by saving overerased cell transistors.
An object of a seventh aspect of the present invention is to provide a semiconductor memory device capable of simultaneously erasing a plurality of blocks of memory cells and easily verifying the erased blocks.
An object of an eighth aspect of the present invention is to provide a semiconductor memory device employing two power sources that are easy to use and operable like a single power source.
An object of a ninth aspect of the semiconductor memory device of the present invention is to provide an inexpensive decoder circuit that solves the problems of the prior art. The decoder circuit of the present invention is simple and compact to achieve the full selection and nonselection of word or bit lines in a test mode. This decoder circuit is suitable for high integration.
According to a first aspect of the present invention, there is provided a semiconductor memory device comprising 2n word lines, a plurality of bit lines, a plurality of nonvolatile memory cells each formed of a MIS transistor disposed at each intersection of the word lines and the bit lines, and a threshold voltage of the MIS transistor being externally electrically controllable, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, a sense amplifier for reading data out of the memory cells, a first unit for simultaneously selecting a block of 2m (n greater than m) word lines among the 2n word lines, and a second unit for not selecting a block of 2k (m greater than k) word lines among the 2m word lines, the second unit not selecting the block of 2k word lines and selecting a block of 2k word lines prepared outside the 2n word lines when any one of the 2k word lines among the 2m word lines is defective.
The selected word lines may receive a negative voltage, and the unselected word lines receive a zero or positive voltage. The block of 2n word lines may form a real cell block, the block of 2m word lines may form an erase block, and the block of 2k word lines outside the block of 2n word lines may form a redundant cell block.
Further, according to a first aspect of the present invention, there is provided a semiconductor memory device comprising 2n word lines, a plurality of bit lines, a plurality of nonvolatile memory cells each formed of a MIS transistor disposed at each intersection of the word lines and the bit lines, and a threshold voltage of the MIS transistor being externally electrically controllable, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, a sense amplifier for reading data out of the memory cells, a first unit for simultaneously selecting a block of 2m (n greater than m) word lines among the 2n word lines, and a second unit for not selecting a block of 2k (m greater than k) word lines among the 2m word lines, data being written to any memory cell transistor, which is contained in the 2k word lines and whose threshold voltage is lower than the potential of an unselected word line, so that the threshold voltage of the memory cell transistor exceeds the potential of the unselected word line, and a block of 2k word lines prepared outside the 2n word lines being used as redundant word lines.
Further, according to a first aspect of the present invention, there is also provided a semiconductor memory device comprising a plurality of word lines, a plurality of bit lines, a plurality of nonvolatile memory cells each formed of a MIS transistor disposed at each intersection of the word lines and the bit lines, and a threshold voltage of the MIS transistor being externally electrically controllable, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, and a sense amplifier for reading data out of the memory cells, wherein each word line is controlled such that a drain current of a memory cell transistor connected to the word line is lower than a channel current thereof, when writing data to the cell transistor to increase the threshold voltage of the memory cell transistor to be higher than the potential of an unselected word line.
Each word line may be controlled by applying a signal in accordance with a pulse signal.
Furthermore, according to a first aspect of the present invention, there is also provided a semiconductor memory device comprising a plurality of word lines, a plurality of bit lines, a plurality of nonvolatile memory cells each formed of a MIS transistor disposed at each intersection of the word lines and the bit lines, and a threshold voltage of the MIS transistor being externally electrically controllable, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, and a sense amplifier for reading data out of the memory cells, wherein an output current of the sense amplifier is changed according to a combination of ON states of two load transistors having different capacities, to realize a normal data read operation, an erase verify operation, and a write verify operation.
A reference voltage may be increased to provide a word line with a voltage, which is used to carry out the write verify or erase verify operations on any cell transistor connected to the word line. P-channel type and n-channel type transistors fabricated in the same process may be connected in series like diodes to provide a word line with a voltage which is used to carry out the write verify or erase verify operations on any cell transistor connected to the word line.
The semiconductor memory device may be constituted by a flash memory.
According to a second aspect of the present invention, there is provided a semiconductor memory device comprising a plurality of real memory cells divided into blocks, a plurality of redundant memory cells to be replaced with defective ones of the real memory cells, a plurality of defective address specifying units for specifying defective addresses of the respective blocks of the real memory cells, and an address comparing unit shared by the defective address specifying unit, for comparing the defective addresses with addresses in the blocks of the real memory cells.
Further, according to a second aspect of the present invention, there is also provided a semiconductor memory device comprising a real cell array having a plurality of memory cells, and a plurality of redundant cells to be replaced with defective memory cells of the real cell array, a redundant information storing cell array for writing data to a defective address according to an externally provided address, a cell selection circuit for selecting the redundant information storing cell array according to the externally provided address, and a read circuit for reading an output of the redundant information storing cell array selected by the cell selection circuit, and providing a redundancy signal.
According to a third aspect of the present invention, there is provided a semiconductor memory device comprising electrically erasable nonvolatile memory cells to and from which data is automatically written and erased according to an internal algorithm incorporated in the semiconductor memory device, wherein the allowable value of write or erase operations is carried out according to the internal algorithm being variable.
According to a fourth aspect of the present invention, there is provided a semiconductor memory device comprising a plurality of word lines, a plurality of bit lines, a plurality of memory cells each formed of a MIS transistor disposed at each intersection of the word lines and the bit lines, and a threshold voltage of the MIS transistor being externally electrically controllable, and a write voltage supply transistor for supplying a write voltage to a drain of the memory cell, wherein the write voltage supply transistor is formed of a p-channel type MIS transistor, which effectively applies the write voltage to the drain of the memory cell.
Further, according to a fourth aspect of the present invention, there is also provided a semiconductor memory device comprising a plurality of word lines, a plurality of bit lines, a plurality of memory cells each formed of a MIS transistor disposed at each intersection of the word lines and the bit lines, and a threshold voltage of the MIS transistor being externally electrically controllable, and a write voltage supply transistor for supplying a write voltage to a drain of the memory cell, wherein the write voltage supply transistor is formed of an n-channel type MIS transistor, and the semiconductor memory device comprises a step-up unit being disposed to increase a gate voltage of the write voltage supply transistor at least up to a sum of the write voltage and a threshold voltage of the write voltage supply transistor.
According to a fifth aspect of the present invention, there is provided a semiconductor memory device comprising a plurality of word lines, a plurality of bit lines, a memory cell array including a plurality of memory cells each formed of a MIS transistor disposed at each intersection of the word lines and the bit lines, a threshold voltage of the MIS transistor being externally electrically controllable according to charges to be injected to a floating gate thereof, and the floating gates of the MIS transistors being simultaneously discharged to collectively erase the memory cells, a first power source for applying a normal selection voltage to a selected word line to select memory cells connected to the word line, when reading data, and a second power source for establishing an unselected state on unselected word lines including memory cells that have been overerased by the collective erasing, when reading data.
Further, according to a fifth aspect of the present invention, there is also provided a semiconductor memory device comprising a plurality of word lines, a plurality of bit lines, a memory cell array including a plurality of memory cells each formed of a MIS transistor disposed at each intersection of the word lines and the bit lines, a threshold voltage of the MIS transistor being externally electrically controllable according to charges to be injected to a floating gate thereof, and the floating gates of the MIS transistors being simultaneously discharged to collectively erase the memory cells, a first row decoder for applying a normal voltage to a selected word line to select memory cells connected to the word line, when reading data, and a second row decoder for applying a predetermined source voltage to the source of each memory cell connected to the selected word line, and applying an unselected state establishing voltage to the sources of memory cells, including those overerased by the collective erasing, connected to unselected word lines, when reading data.
According to a sixth aspect of the present invention, there is provided a semiconductor memory device comprising a plurality of word lines, a plurality of bit lines, a memory cell array including a plurality of memory cells each formed of a MIS transistor disposed at each intersection of the word lines and the bit lines, a threshold voltage of the MIS transistor being externally electrically controllable according to charges to be injected to a floating gate thereof, and the floating gates of the MIS transistors being simultaneously discharged to collectively erase the memory cells, wherein a method of saving overerased memory cells of the semiconductor memory device detects memory cells that have been overerased by the collective erasing, and writing data to the overerased memory cells, thereby saving the overerased memory cells.
Further, according to a sixth aspect of the present invention, there is also provided a semiconductor memory device comprising a plurality of word lines, a plurality of bit lines, a memory cell array including a plurality of memory cells each formed of a MIS transistor disposed at each intersection of the word lines and the bit lines, and a threshold voltage of the MIS transistor being externally electrically controllable according to charges to be injected to a floating gate thereof, a write-before-erase unit for writing all memory cells of the memory cell array before erasing them, an erase unit for erasing all of the written memory cells by the write-before-erase unit and for verifying the erasing, an overerased cell detecting unit for detecting overerased memory cells among the erased and verified memory cells by the erase unit, and an overerased cell saving unit for writing the overerased memory cells detected by the overerased cell detecting unit, thereby saving the overerased memory cells.
According to a seventh aspect of the present invention, there is provided a semiconductor memory device comprising a plurality of word lines, a plurality of bit lines, and a plurality of nonvolatile memory cells each formed of a MIS transistor disposed at each intersection of the word lines and the bit lines, and a threshold voltage of the MIS transistor being externally electrically controllable, wherein the nonvolatile memory cells areg divided into a plurality of cell blocks to be selected according to a block selection signal provided by a block address buffer, each of the cell blocks has a data erasing unit and a latching unit for latching the block selection signal, and thereby data of the cell blocks that have latched the block selection signal are simultaneously erased.
According to an eighth aspect of the present invention, there is provided a semiconductor memory device comprising a first terminal for receiving a normal voltage, a second terminal for receiving a high voltage from a high-voltage supply unit, and the high voltage being required to write or erase data and higher than the normal voltage required to read data, a third terminal for providing the high-voltage supply unit with a control signal that controls the supply of the high voltage.
Further, according to an eighth aspect of the present invention, there is also provided a semiconductor memory device comprising a step-up circuit for supplying a high voltage that is required to write or erase data and higher than a normal voltage required to read data, a command determination unit that determines whether or not an operation specified by an input command to the semiconductor memory device requires the high voltage, and provides a control signal to start the supply of the high voltage if the operation requires the high voltage, and if not, a control signal to stop the high voltage.
Furthermore, according to an eighth aspect of the present invention, there is also provided a computer system having a semiconductor memory device as a part of a storage unit and a step-up circuit for generating a high voltage required to write and erase data to and from the semiconductor memory device, wherein the computer system comprises a control unit for automatically generating a control signal to control the step-up circuit, in response to an access operation to the semiconductor memory device.
According to a ninth aspect of the present invention, there is provided a semiconductor memory device comprising a plurality of word lines, a plurality of bit lines, a plurality of memory cells disposed at each intersection of the word lines and the bit lines, and a decoder circuit for selecting the memory cell according to an address signal in a normal decoding function and for carrying out a full selection operation or a nonselection operation of the word lines or the bit lines in a test function, and an output row or a decoding row connected to a first power source and a second power source, the first power source supplying a high voltage, and the second power source supplying a reference voltage or the high voltage in response to a control signal.
Further, according to a ninth aspect of the present invention, there is also provided a semiconductor memory device comprising a plurality of word lines, a plurality of bit lines, a plurality of memory cells disposed at each intersection of the word lines and the bit lines, a decoder circuit for selecting the memory cell according to an address signal in a normal decoding function and for carrying out a full selection operation or a nonselection operation of the word lines or the bit lines in a test function, and an output row or a decoding row connected to a first power source and a second power source, the first power source supplying a reference voltage, and the second power source supplying a reference voltage or the high voltage in response to a control signal.